Commonly Used Stack-Ups for HDI Multilayer PCBs: Design, Benefits, and Applications

High-Density Interconnect (HDI) multilayer PCBs have become the backbone of cutting-edge electronics—from 5G smartphones to medical implants—by packing more components, faster signals, and complex functionality into smaller footprints. But the success of these advanced PCBs hinges on one critical design decision: the layer stack-up. A well-engineered stack-up optimizes signal integrity, thermal management, and manufacturability, while a poor one can cripple performance, cause crosstalk, or lead to costly rework.

This guide breaks down the most commonly used HDI multilayer PCB stack-ups, explains how to choose the right configuration for your application, and outlines key design principles to avoid pitfalls. Whether you’re designing a 6-layer smartphone PCB or a 12-layer 5G base station board, understanding these stack-ups will help you unlock the full potential of HDI technology.

Key Takeaways
1.HDI multilayer PCB stack-ups (4–12 layers) use microvias (50–150μm) and staggered/stacked vias to achieve 2–3x higher component density than traditional multilayer PCBs.
2.The most common configurations are 2+2+2 (6-layer), 4+4 (8-layer), 1+N+1 (flexible layer count), and 3+3+3 (9-layer), each tailored to specific density and performance needs.
3.A well-designed stack-up reduces signal loss by 40% at 28GHz, cuts crosstalk by 50%, and lowers thermal resistance by 30% compared to haphazard layer layouts.
4.Industries like consumer electronics, telecom, and medical devices rely on specialized stack-ups: 2+2+2 for smartphones, 4+4 for 5G base stations, and 1+N+1 for wearables.

What Is an HDI Multilayer PCB Stack-Up?
An HDI multilayer PCB stack-up is the arrangement of conductive copper layers (signal, power, ground) and insulating dielectric layers (substrate, prepreg) in a PCB. Unlike traditional multilayer PCBs— which rely on through-hole vias and simple “signal-ground-signal” layouts—HDI stack-ups use:
  a.Microvias: Tiny holes (50–150μm diameter) that connect adjacent layers (blind vias: outer → inner; buried vias: inner → inner).
  b.Stacked/staggered vias: Microvias stacked vertically (stacked) or offset (staggered) to connect non-adjacent layers without through-holes.
  c.Dedicated planes: Separate ground and power layers to minimize noise and improve signal integrity.
The goal of an HDI stack-up is to maximize density (components per square inch) while maintaining high-speed signal performance (25Gbps+) and thermal efficiency—critical for compact, high-power devices.

Why Stack-Up Design Matters for HDI Multilayer PCBs
A poorly designed stack-up undermines even the most advanced HDI features. Here’s why it’s make-or-break:
  1.Signal Integrity: High-speed signals (28GHz 5G, 100Gbps data center links) are sensitive to impedance mismatches and crosstalk. A proper stack-up (e.g., signal layer adjacent to ground plane) maintains controlled impedance (50Ω/100Ω) and reduces signal reflection by 30%.
  2.Thermal Management: Dense HDI PCBs generate heat—dedicated copper planes in the stack-up spread heat 2x faster than traditional layouts, lowering component temperatures by 25°C.
  3.Manufacturability: Overly complex stack-ups (e.g., 12 layers with 100μm microvias) increase scrap rates to 15%; optimized designs keep scrap <5%.
  4.Cost Efficiency: Choosing a 6-layer stack-up instead of 8-layer for a smartphone PCB cuts material costs by 25% without sacrificing performance.

Most Commonly Used HDI Multilayer PCB Stack-Ups
HDI stack-ups are categorized by their layer count and microvia configuration. Below are the four most widely adopted designs, with use cases, benefits, and limitations.

1. 2+2+2 (6-Layer) HDI Stack-Up
The 2+2+2 stack-up is the “workhorse” of consumer electronics, balancing density, performance, and cost. It consists of:
  a.Top sub-stack: 2 layers (Top Signal + Inner 1 Ground) connected by blind microvias.
  b.Middle core: 2 layers (Inner 2 Power + Inner 3 Signal) connected by buried microvias.
  c.Bottom sub-stack: 2 layers (Inner 4 Ground + Bottom Signal) connected by blind microvias.
Key Features:
  a.Uses stacked microvias (Top → Inner 1 → Inner 2) to connect outer and middle layers.
  b.Dedicated ground planes adjacent to signal layers reduce crosstalk.
  c.Supports 0.4mm pitch BGAs and 0201 passives—ideal for compact devices.
Performance Metrics:
  a.Signal loss at 28GHz: 1.8dB/inch (vs. 2.5dB/inch for traditional 6-layer PCBs).
  b.Component density: 800 components/square inch (2x traditional 6-layer).
Best For:
  a.Smartphones (e.g., iPhone 15 main PCB), tablets, wearables (smartwatches), and IoT sensors.
Pros & Cons:

2. 4+4 (8-Layer) HDI Stack-Up
The 4+4 stack-up is the go-to for mid-range high-performance devices, adding two more layers to the 2+2+2 design for extra signal and power paths. It features:
  a.Top sub-stack: 4 layers (Top Signal 1, Inner 1 Ground, Inner 2 Power, Inner 3 Signal 2) connected by stacked microvias.
  b.Bottom sub-stack: 4 layers (Inner 4 Signal 3, Inner 5 Ground, Inner 6 Power, Bottom Signal 4) connected by stacked microvias.
  c.Buried vias: Connect Inner 3 (Top sub-stack) to Inner 4 (Bottom sub-stack) for cross-stack signal routing.
Key Features:
  a.Four dedicated signal layers (supports 4x 25Gbps paths).
  b.Dual power planes (e.g., 3.3V and 5V) for multi-voltage systems.
  c.Uses laser-drilled microvias (75μm diameter) for high precision.
Performance Metrics:
  a.Impedance control: ±5% (critical for 5G mmWave).
  b.Thermal resistance: 0.8°C/W (vs. 1.2°C/W for 6-layer stack-up).
Best For:
  a.5G small cells, mid-range smartphones (e.g., Samsung Galaxy A series), industrial IoT gateways, and automotive ADAS sensors.
Pros & Cons:

3. 1+N+1 (Flexible Layer Count) HDI Stack-Up
The 1+N+1 stack-up is a modular design where “N” is the number of inner layers (2–8), making it versatile for custom needs. It’s structured as:
  a.Top layer: 1 signal layer (blind microvias to Inner 1).
  b.Inner layers: N layers (mix of signal, ground, power—e.g., 2 ground, 2 power for N=4).
  c.Bottom layer: 1 signal layer (blind microvias to Inner N).
Key Features:
  a.Customizable inner layer count (e.g., 1+2+1=4-layer, 1+6+1=8-layer).
  b.Staggered microvias (instead of stacked) for simpler manufacturing in low-volume runs.
  c.Ideal for prototyping or designs with unique power/signal needs.
Performance Metrics:
  a.Signal loss: 1.5–2.2dB/inch (varies by N; lower for more ground planes).
  b.Component density: 600–900 components/square inch (increases with N).
Best For:
  a.Prototypes (e.g., startup IoT devices), medical wearables (e.g., glucose monitors), and low-volume industrial sensors.
Pros & Cons:

4. 3+3+3 (9-Layer) HDI Stack-Up
The 3+3+3 stack-up is a high-performance design for complex systems, with three equal sub-stacks:
  a.Top sub-stack: 3 layers (Top Signal 1, Inner 1 Ground, Inner 2 Power) → blind microvias.
  b.Middle sub-stack: 3 layers (Inner 3 Signal 2, Inner 4 Ground, Inner 5 Signal 3) → buried microvias.
  c.Bottom sub-stack: 3 layers (Inner 6 Power, Inner 7 Ground, Bottom Signal 4) → blind microvias.
Key Features:
  a.Triple ground planes (maximizes noise reduction).
  b.Supports 4+ high-speed differential pairs (100Gbps+).
  c.Uses copper-filled microvias for power paths (carries 5–10A per via).
Performance Metrics:
  a.Signal loss at 40GHz: 2.0dB/inch (best-in-class for HDI).
  b.Crosstalk: <-40dB (vs. <-30dB for 8-layer stack-up).
Best For:
  a.5G macro base stations, data center transceivers (100Gbps+), aerospace avionics, and high-end medical imaging devices.
Pros & Cons:

Comparison of Common HDI Stack-Ups
Use this table to quickly evaluate which stack-up fits your project’s needs:

Key Design Principles for HDI Multilayer PCB Stack-Ups
Even the best stack-up configuration fails without proper design. Follow these principles to optimize performance:
1. Pair Signal Layers with Ground Planes
Every high-speed signal layer (≥1Gbps) must be adjacent to a solid ground plane. This:
  a.Reduces loop area (a major source of EMI) by 50%.
  b.Maintains controlled impedance (e.g., 50Ω for single-ended signals) by ensuring consistent dielectric thickness between the signal trace and ground.
Example: In a 2+2+2 stack-up, placing Top Signal (28GHz) directly above Inner 1 Ground cuts signal reflection by 30% vs. a signal layer with no adjacent ground.

2. Separate Power and Signal Layers
Power planes generate noise (voltage ripple, switching transients) that interferes with high-speed signals. To mitigate this:
  a.Place power planes on the opposite side of ground planes from signal layers (e.g., Signal → Ground → Power).
  b.Use separate power planes for different voltage levels (e.g., 3.3V and 5V) to avoid cross-talk between power domains.
  c.Add decoupling capacitors (01005 size) between power planes and signal layers to suppress noise.
Data: Separating power and signal layers with a ground plane reduces power-related noise by 45% in 10Gbps designs.

3. Optimize Microvia Placement
Microvias are critical for HDI density but can cause signal issues if misplaced:
  a.Stacked Vias: Use for high-density designs (e.g., smartphones) but limit to 2–3 layers (stacking 4+ layers increases void risk).
  b.Staggered Vias: Use for low-volume or high-reliability designs (e.g., medical devices)—they’re easier to manufacture and have fewer voids.
  c.Keep Vias Away from Trace Corners: Place microvias ≥0.5mm from trace bends to avoid impedance spikes.

4. Balance Thermal and Electrical Needs
High-density HDI PCBs trap heat—design the stack-up to dissipate it:
  a.Use 2oz copper for power planes (vs. 1oz) to improve thermal conductivity.
  b.Add thermal vias (copper-filled, 0.3mm diameter) between hot components (e.g., 5G PA modules) and inner ground planes.
  c.For 10W+ devices, include a metal core layer (aluminum or copper) in the stack-up (e.g., 2+1+2+1+2=8-layer with 1 metal core).
Case Study: A 4+4 stack-up with 2oz power planes and 12 thermal vias reduced a 5G PA module’s temperature by 20°C vs. a 1oz design.

5. Follow IPC-2226 Standards
IPC-2226 (the global standard for HDI PCBs) provides critical guidelines for stack-ups:
  a.Minimum microvia diameter: 50μm (laser-drilled).
  b.Minimum distance between microvias: 100μm.
  c.Dielectric thickness between layers: 50–100μm (for controlled impedance).
Adhering to IPC-2226 ensures your stack-up is manufacturable and meets industry reliability standards

Material Selection for HDI Stack-Ups

The right materials enhance stack-up performance—choose based on your signal speed and environment:

Common Stack-Up Challenges and Solutions
Even with careful design, HDI stack-ups face unique hurdles. Here’s how to overcome them:

Real-World Applications of HDI Stack-Ups
1. Consumer Electronics: Smartphones
  a.Device: iPhone 15 Pro Main PCB
  b.Stack-Up: 2+2+2 (6-layer)
  c.Why: Balances density (1,200 components/sq. inch) and cost; stacked microvias enable 0.35mm pitch BGAs for the A17 Pro chip.
  d.Result: 30% smaller PCB than iPhone 13, with 2x faster 5G speeds (4.5Gbps download).

2. Telecom: 5G Small Cells
  a.Device: Ericsson 5G Radio Unit
  b.Stack-Up: 4+4 (8-layer)
  c.Why: Four signal layers handle 28GHz mmWave and 4G LTE signals; dual power planes support 20W amplifiers.
  d.Result: 40% lower signal loss than traditional 8-layer PCBs, extending small cell range by 25%.

3. Medical: Portable Ultrasound
  a.Device: GE Healthcare Logiq E Ultrasound Probe
  b.Stack-Up: 1+4+1 (6-layer)
  c.Why: Modular design fits custom sensor needs; polyimide substrate withstands sterilization (134°C).
  d.Result: 50% lighter probe than previous models, with clearer imaging (thanks to low crosstalk).

4. Automotive: ADAS Radar
  a.Device: Tesla Autopilot Radar Module
  b.Stack-Up: 3+3+3 (9-layer)
  c.Why: Triple ground planes reduce EMI from car electronics; copper-filled vias handle 15A power for radar transmitters.
  d.Result: 99.9% detection accuracy in rain/fog, meeting ISO 26262 safety standards.

FAQs About HDI Multilayer PCB Stack-Ups
Q: How do I choose between a 2+2+2 and 4+4 stack-up?
A: Use 2+2+2 if your design needs ≤2 high-speed paths (e.g., smartphone with 5G + Wi-Fi 6E) and prioritizes cost. Choose 4+4 for 3+ high-speed paths (e.g., 5G small cell with 28GHz + 39GHz) or 10W+ power dissipation.

Q: Can HDI stack-ups support flexible PCBs?
A: Yes—use a 1+N+1 stack-up with polyimide substrate (e.g., 1+2+1=4-layer flexible HDI). This is common in foldable phones (hinge areas) and wearables.

Q: What’s the minimum layer count for a 5G mmWave PCB?
A: 6 layers (2+2+2) with Rogers RO4350 substrate. Fewer layers (4-layer) cause excessive signal loss (>2.5dB/inch at 28GHz).

Q: How much does an HDI stack-up add to PCB cost?
A: A 2+2+2 stack-up costs 30% more than a traditional 6-layer PCB; a 3+3+3 stack-up costs 2x more. The premium is offset by smaller device size and better performance.

Q: Do I need special software to design HDI stack-ups?
A: Yes—tools like Altium Designer, Cadence Allegro, and Mentor Xpedition have HDI-specific features: microvia design rules, impedance calculators, and stack-up simulators.

Conclusion
HDI multilayer PCB stack-ups are the unsung heroes of modern electronics, enabling the compact, high-performance devices we rely on daily. The 2+2+2, 4+4, 1+N+1, and 3+3+3 configurations each serve unique needs—from budget-friendly smartphones to mission-critical 5G base stations.
The key to success is matching the stack-up to your application: prioritize cost with 2+2+2, performance with 3+3+3, and flexibility with 1+N+1. Pair this with smart design principles (signal-ground pairing, microvia optimization) and high-quality materials, and you’ll create HDI PCBs that excel in density, speed, and reliability.

As electronics continue to shrink and speeds climb to 60GHz+ (6G), HDI stack-up design will only grow in importance. By mastering these configurations and best practices, you’ll be ready to build the next generation of cutting-edge devices—ones that are smaller, faster, and more efficient than ever before.